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1. general description the lpc111xlv/lpc11xxlvuk is an arm cortex-m0-based, low-cost 32-bit mcu family, designed for 8/16-bit microcontroller applications , offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. the lpc111xlv/lpc11xxlvuk operate at cpu frequencies of up to 50 mhz. the peripherals of the lpc111xlv/lpc11xxlvuk include up to 32 kb of flash memory, up to 8 kb of sram data memory, a fast-mode plus i 2 c-bus interfac e, one ssp/spi interface, one uart, four general-purpose co unter/timers, an 8-bit adc, and up to 27 general-purpose i/o pins. 2. features and benefits ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug. ? system tick timer. ? memory: ? up to 32 kb on-chip flash programming memory with a 256 byte page erase function. ? up to 8 kb sram. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? digital peripherals: ? up to 27 general-purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors and a configurable open-drain mode. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current output driver on one pin. ? high-current sink drivers on two i 2 c-bus pins in fast-mode plus. ? four general-purpose counter/timers with up to 7 capture inputs and 13 match outputs. ? programmable windowed wdt. ? analog peripherals: 8-bit adc with input multiplexing among up to 8 pins. ? serial interfaces: lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 mcu; up to 32 kb flash, 8 kb sram; 8-bit adc rev. 2 ? 10 october 2012 product data sheet www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 2 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller ? uart with fractional baud rate generation and internal fifo. ? one spi controller with ssp f eatures and with fi fo and multi-prot ocol capabilities. ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address reco gnition and monitor mode. ? clock generation: ? 12 mhz internal rc oscillator trimmed to 2.5 % accuracy for t amb = -20 c to +85 c and to 5 % accuracy for t amb = -40 c to -20 c. the irc can optionally be used as a system clock. ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? programmable watchdog oscillator with a frequency range of 9.4 khz to 2.3 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? clock output function with divider that ca n reflect the system oscillator clock, irc clock, cpu clock, and the watchdog clock. ? power control: ? two reduced power modes: sleep and deep-sleep mode. ? ultra-low power consumption in deep-sleep mode ( ? 1.6 ? a). ? 5 ? s wake-up time from deep-sleep mode. ? processor wake-up from deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. ? power-on reset (por). ? brown-out detection (bod) causing a forced reset. ? unique device serial number for identification. ? single power supply (1.65 v to 1.95 v) ? available as wlcsp25, hvqfn24, and hv qfn33 package. other package options are available for high-volume customers. 3. applications 4. ordering information ? mobile phones ? tablets/ultra books ? mobile accessories ? active cables ? cameras ? portable medical electronics table 1. ordering information type number package name description version lpc1101lvuk wlcsp25 wafer level chip-size package; 25 bumps; 2.17 ? 2.32 ? 0.56 mm - lpc1102lvuk wlcsp25 wafer level chip-size package; 25 bumps; 2.17 ? 2.32 ? 0.56 mm - lpc1112lvfhn24/003 hvqfn24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm sot616-3 lpc1114lvfhn24/103 hvqfn24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm sot616-3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 3 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 4.1 ordering options lpc1114lvfhn24/303 hvqfn24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm sot616-3 lpc1112lvfhi33/103 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc1114lvfhi33/303 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a table 1. ordering information ?continued type number package name description version table 2. ordering options type number flash in kb total sram in kb spi/ ssp i2c uart adc gpi o pins package lpc1101lvuk 32 2 1 1 1 6-channel 21 wlcsp25 lpc1102lvuk 32 8 1 1 1 6-channel 21 wlcsp25 lpc1112lvfhn24/003 16 2 1 1 1 6-channel 20 hvqfn24 lpc1114lvfhn24/103 32 4 1 1 1 6-channel 20 hvqfn24 lpc1114lvfhn24/303 32 8 1 1 1 6-channel 20 hvqfn24 lpc1112lvfhi33/103 16 4 1 1 1 8-channel 27 hvqfn33 lpc1114lvfhi33/303 32 8 1 1 1 8-channel 27 hvqfn33 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 4 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 5. block diagram (1) ct16b1_mat1, ct32b1_cap1, ct1b0_cap1, ct16b1_cap1 available on hvqfn33 only. ct16b1_mat0 available on hvqfn33 and wlcsp25 packages only. (2) 6 channels on wlcsp25 and hvqfn24 packages. 8 channels on hvqfn33 packages. (3) dsr on wlcsp25 package only. dtr on hvqfn33 package only. cts on hvqfn24 and hvqfn33 packages only. fig 1. lpc111xlv/lpc11xxlvuk block diagram sram 2/4/8 kb arm cortex-m0 test/debug interface flash 16/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout reset clocks and controls swd lpc110xlvuk lpc111xlv 002aag851 slave slave slave slave rom slave ahb-lite bus gpio ports clkout irc por spi0 10-bit/8-bit adc (2) uart 32-bit counter/timer 0 i 2 c-bus wwdt iocon ct32b0_mat[3:0] ad[7:0] ct32b0_cap0 sda scl rxd txd dsr (3) , rts, cts (3) , dtr (3) system control 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap[1:0] (1) 16-bit counter/timer 1 ct16b1_mat[1:0] (1) ct16b1_cap[1:0] (1) 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap[1:0] (1) sck0, ssel0 miso0, mosi0 system bus www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 5 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning fig 2. pin configuration wlcsp25 package a b c d e ball a1 index area lpc1101/02lvuk 002aag852 transparent top view 12345 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 6 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller for parts lpc1112lvfhn24/003, lpc1114lvfhn24/103, lpc1114lvfhn24/303. fig 3. pin configuration hvqfn24 package 002aag849 transparent top view pio0_9/mosi0/ct16b0_mat1 xtalout pio1_8/ct16b1_cap0 swclk/pio0_10/sck0/ct16b0_mat2 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio1_7/txd/ct32b0_mat1 r/pio1_2/ad3/ct32b1_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_4/scl pio0_5/sda pio0_6/sck0 pio0_7/cts pio0_8/miso0/ct16b0_mat0 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd v ss pio1_4/ad5/ct32b1_mat3 swdio/pio1_3/ad4/ct32b1_mat2 terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 7 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller for parts lpc1112lvfhi33/103 and lpc1114lvfhi33/303. fig 4. pin configuration hvqfn33 package 002aag850 transparent top view pio0_8/miso0/ct16b0_mat0 pio1_8/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1 v dd(io) swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio1_10/ad6/ct16b1_mat1 xtalin r/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio2_0/dtr r/pio1_2/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio1_9/ct16b1_mat0 pio3_4/ct16b0_cap1/rxd pio3_5/ct16b1_cap1/txd pio0_6/sck0 pio0_7/cts pio1_7/txd/ct32b0_mat1 pio1_6/rxd/ct32b0_mat0 pio1_5/rts/ct32b0_cap0 v dd v dd(io) pio1_11/ad7/ct32b1_cap1 pio1_4/ad5/ct32b1_mat3 swdio/pio1_3/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 8 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 6.2 pin description table 3. lpc110xlvuk/lpc111xlv pin description table symbol wlcsp25 hvqfn24 hvqfn33 start logic input type reset state [1] description reset /pio0_0 d1 2 2 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and proc essor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 c3 3 3 [3] yes i/o i; pu pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 b2 7 8 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 - - 9 [3] yes i/o i;pu pio0_3 ? general purpose digital input/output pin. pio0_4/scl a2 8 10 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda a3 9 11 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 a4 10 15 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts -1116 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 a5 12 17 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 b5 13 18 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 9 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller swclk/pio0_10/ sck0/ ct16b0_mat2 b4 14 19 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ct32b0_mat3 c5 15 21 [5] yes i i; pu r ? reserved. configure for an alternate function in the iocon block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. r/pio1_0/ ad1/ct32b1_cap0 c4 16 22 [5] yes i i; pu r ? reserved. configure for an alternate function in the iocon block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ ad2/ct32b1_mat0 d5 17 23 [5] no o i; pu r ? reserved. configure for an alternate function in the iocon block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ ad3/ct32b1_mat1 d4 18 24 [5] no i i; pu r ? reserved. configure for an alternate function in the iocon block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ct32b1_mat2 e5 19 25 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3 d3 20 26 [5] no i/o i; pu pio1_4 ? general purpose digital input/output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. pio1_5/rts / ct32b0_cap0 e2 23 30 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 d2 24 31 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. table 3. lpc110xlvuk/lpc111xlv pin description table symbol wlcsp25 hvqfn24 hvqfn33 start logic input type reset state [1] description www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 10 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled (pins pulled up to full v dd level 0; ia = inactive, no pull-up/down enabled. [2] see figure 28 for the reset pad configuration. [3] pad providing digital i/o functions with configurable pull-up/pull-down resi stors and configurable hysteresis (see figure 27 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] pad providing digital i/o functions with configurable pull-up/pull-down resistor s, configurable hysteresis, and analog input . when configured as an adc input, digital section of the pad is disabled (see figure 27 ). [6] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio1_7/txd/ ct32b0_mat1 e1 1 32 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 b1 6 7 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 b3 - 12 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 --20 [5] no i/o i;pu pio1_10 ? general purpose digital input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7/ ct32b0_mat3 --27 [5] no i/o i;pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio2_0/dtr --1 [3] no i/o i;pu pio2_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio2_1/dsr a1 - - [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. pio3_4/ ct16b0_cap1/rxd --13 [3] no i/o i;pu pio3_4 ? general purpose digital input/output pin. i- ct16b0_cap1 ? capture input 1 for 16-bit timer 0. i- rxd ? receiver input for uart. pio3_5/ ct16b1_cap1/txd --14 [3] no i/o i;pu pio3_5 ? general purpose digital input/output pin. i- ct16b1_cap1 ? capture input 1 for 16-bit timer 1. o- txd ? transmitter output for uart. v dd e3 22 29; 6; 28 - - - 1.8 v supply voltage to the core, the external rail, and the adc. also used as the adc reference voltage. xtalin c1 4 4 [6] - i - input to the oscillator circuit and internal clock generator circuits. input vo ltage must not exceed 1.8 v. xtalout c2 5 5 [6] - o - output from the oscillator amplifier. v ss e4 21 33 - - - ground. table 3. lpc110xlvuk/lpc111xlv pin description table symbol wlcsp25 hvqfn24 hvqfn33 start logic input type reset state [1] description www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 11 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7. functional description 7.1 arm cortex-m0 processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 on-chip flash program memory the lpc111xlv/lpc11xxlvuk contains up to 32 kb of on-chip flash memory. the flash memory is divided into 4 kb sector s with each sector consisting of 16 pages. individual pages of 256 byte each can be erased using the iap erase page command. 7.3 on-chip sram the lpc111xlv/lpc11xxlvuk contains up to 8 kb on-chip static ram memory. 7.4 memory map the lpc111xlv/lpc11xxlvuk incorporates several distinct memory regions, shown in the following figures. figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 megabyte in si ze, and is divided to allow for up to 128 peripherals. the apb peripheral ar ea is 512 kb in size and is divided to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kilobytes of space. this allows simplifying the address decoding for each peripheral. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 12 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7.5 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.5.1 features ? controls system exceptions and peripheral interrupts. fig 5. lpc111xlv/lpc11xxlvuk memory map 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 127-16 reserved gpio pio1 7-4 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 11-8 15-12 gpio pio0 3-0 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart reserved i 2 c-bus 13-10 reserved reserved reserved reserved 21-19 reserved 31-23 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 0800 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved apb peripherals ahb peripherals 0x1000 0000 2 kb sram lpc1101lvuk, lpc1112lv/003 0x1000 1000 0x1000 2000 4 kb sram lpc1114lv/103, lpc1112lv/103 8 kb sram lpc1114lv/303, lpc1102lvuk lpc110xlvuk lpc111xlv 0x0000 8000 32 kb on-chip flash lpc1101lvuk, lpc1102lvuk lpc1114lv 0x0000 4000 16 kb on-chip flash lpc1112lv 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aag853 reserved spi0 16-bit counter/timer 1 16-bit counter/timer 0 iocon system control 22 flash controller 0xe000 0000 0xe010 0000 private peripheral bus www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 13 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller ? in the lpc111xlv/lpc11xxlvuk, the nvic s upports 32 vectored interrupts including up to 13 inputs to the start logic from individual gpio pins. ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interr upt generation. 7.5.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any gpio pin (total of up to 18 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 iocon block the iocon block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc111xlv/lpc11xxlvuk use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. additionally, any gpio pin (total of up to 18 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 features ? bit level port registers allow a single instruct ion to set or clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to inputs with pull-ups enabled after reset with the exception of the i 2 c-bus pins pio0_4 and pio0_5. ? pull-up/pull-down resistor configuration can be programmed through the iocon block for each gpio pin (except for pins pio0_4 and pio0_5). ? all gpio pins (except pio0_4 and pio0_5) are pulled up to 1.8 v (v dd = 1.8 v) if their pull-up resistor is enabled in the iocon block (single power supply). ? programmable open-drain mode. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 14 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7.8 uart the lpc111xlv/lpc11xxlvuk contains one uart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the uart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.8.1 features ? maximum uart data bit rate of 3.125 mbit/s. ? 16 byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. 7.9 spi serial i/o controller the lpc111xlv/lpc11xxlvuk contains one spi controller. the spi controller is capable of operation on an ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the spi supports full-duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.9.1 features ? maximum spi speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ssp mode) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.10 i 2 c-bus serial i/o controller the lpc111xlv/lpc11xxlvuk contains one i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 15 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 features ? the i 2 c-interface is a standard i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface also supports fast-mod e plus with bit rates up to 1 mbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.11 adc the lpc111xlv/lpc11xxlvuk contains one adc. it is a single 8-bit successive approximation adc with up to eight channels. remark: adc specifications are valid for t amb = -40 c to +85 c on hvqfn33 and wlcsp25 packages. adc specifications are valid for t amb = -10 c to 85 c on the hvqfn24 package. 7.11.1 features ? 8-bit successive approximation adc. ? input multiplexing among 6 pins (wlcsp25 and hvqfn24 packages). ? input multiplexing among 8 pins (hvqfn33 packages). ? power-down mode. ? measurement range 0 v to v dd . ? 8-bit sampling rate of up to 10 ksamples/s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 16 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7.12 general purpose externa l event counter/timers the lpc111xlv/lpc11xxlvuk includes two 32-bit counter/timers and two 16-bit counter/timers. the counter/time r is designed to count cycles of the system derived clock. it can optionally generate interrupts or perf orm other actions at specified timer values, based on four match registers. each counter/ti mer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.12.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 7.13 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.14 windowed watchdog timer the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.14.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 17 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the irc or the dedicated watchdog oscillator (wdo). this gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.15 clocking and power control 7.15.1 crystal oscillators the lpc111xlv/lpc11xxlvuk include three independent oscillato rs. these are the system oscillator, the internal rc oscillato r (irc), and the watchdog oscillator. each oscillator can be used for more than one purpo se as required in a pa rticular application. following reset, the lpc111xlv/ lpc11xxlvuk will operate from the internal rc oscillator until switched by software. this allows system s to operate without any external crystal and the bootloader code to oper ate at a known frequency. see figure 6 for an overview of the lpc111xlv/lpc11xxlvuk clock generation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 18 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7.15.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 2.5 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc 111xlv/lpc11xxlvuk use the irc as the clock source. software may later switch to one of the other available clock sources. 7.15.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. fig 6. lpc111xlv/lpc11xxlvuk clock generation block diagram system pll irc oscillator system oscillator watchdog oscillator irc oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) system clock divider ahb clock 0 (system) sysahbclkctrl[1:18] (ahb clock enable) ahb clocks 1 to 18 (memories and peripherals) spi0 peripheral clock divider spi0 uart peripheral clock divider uart wwdt clock divider wdt wdtuen (wdt clock update enable) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aag859 main clock system clock irc oscillator 18 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 19 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7.15.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 9.4 khz and 2.3 mhz. th e frequency spread over processing and temperature is ? 40 %. 7.15.2 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is prov iding the desired output frequency. the pll output frequency must be lower than 100 mhz. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. si nce the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.15.3 clock output the lpc111xlv/lpc11xxlvuk features a cloc k output function t hat routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.15.4 wake-up process the lpc111xlv/lpc11xxlvuk begin operation at power-up by using the 12 mhz irc oscillator as the clock source. this allows ch ip operation to resume quickly. if the system oscillator or the pll is needed by the applic ation, software will n eed to enable these features and wait for them to stabilize before they are used as a clock source. 7.15.5 power control the lpc111xlv/lpc11xxlvuk support a variety of power control features. there are two special modes of processor power reduction: sleep mode, and deep-sleep mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutti ng down the clocks to individual on-chip peripherals, allowing fine-tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required fo r the application. selected peripherals have their own clock divider which prov ides even better power control. 7.15.5.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 20 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 7.15.5.2 deep-sleep mode in deep-sleep mode, the chip is in sleep mode, and in addition all analog blocks are shut down. as an exception, the user has the opt ion to keep the irc, the bod, and the watchdog timer/watchdog oscilla tor running for self-timed wake-up. deep-sleep mode allows for additional power savings. up to 13 pins can serve as external wake-up pins to the start logic to wake up the chip from deep-sleep mode. unless the watchdog oscillator or the irc ar e selected to run in deep-sleep mode, the clock source should be switched to irc before entering deep-sleep mode, because the irc can be switched on and off glitch-free. 7.16 system control 7.16.1 start logic the start logic connects external pins to corresponding interrupts in the nvic. each pin shown in ta b l e 3 as input to the start logic is connec ted to an individual interrupt in the nvic interrupt vector table. the start logic pi ns can serve as external interrupt pins when the chip is in active mode. in addition, an input signal on the start logic pins can wake up the chip from deep-sleep mode when all clocks are shut down. the start logic must be configured in the system configuration block and in the nvic before being used. 7.16.2 reset reset has four sources on the lpc111xlv/lpc11xxlvuk: the reset pin, the watchdog reset, the brownout detection (bod) circui t, and power-on re set (por). the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts th e irc and initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. 7.16.3 brownout detection (bod) the lpc111xlv/lpc11xxlvuk includes a bod circuit which monitors the voltage level on the v dd pin. if this voltage falls below a fixed level (see ta b l e 8 ), the bod asserts a chip reset. 7.16.4 code security (code read protection - crp) this feature of the lpc111xlv/lpc11xxlvuk allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details see the lpc111xlv user manual . www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 21 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 select ed fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via the uart. in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled (no_isp mode). for details see the lpc111xlv user manual . 7.16.5 apb interface the apb peripherals are located on one apb bus. 7.16.6 ahblite the ahblite connects the cpu bus of the arm cortex-m0 to the flash memory, the main static ram, and the boot rom. 7.16.7 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. in addition, start logic inputs serve as external interrupts (see section 7.16.1 ). 7.17 emulation and debugging debug functions are integrated into the arm cortex-m0. serial wire debug with four breakpoints and two watchpoints is supported. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 22 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. refer to the je dec spec (j-std-033b.1) for further details. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) 1.65 1.95 v v i input voltage only valid when the v dd supply voltage is present 1.65 v ? v dd < 1.8 v [2] ? 0.5 +3.0 v v dd ? 1.8 v ? 0.5 +5.0 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ?c -100ma t stg storage temperature non-operating [3] ? 65 +150 ? c t j(max) maximum junction temperature - 150 ? c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [4] ? 6500 +6500 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 23 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 9. static characteristics 9.1 static characteristics table 5. static characteristics (single power supply t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) 1.65 1.8 1.95 v power consumption i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz v dd = 1.8 v [2] [3] [4] [5] -2-m a system clock = 50 mhz v dd = 1.8 v [2] [3] [5] [6] -8-m a sleep mode; system clock = 12 mhz v dd = 1.8 v [2] [3] [4] [5] -0 . 8-m a deep-sleep mode; v dd = 1.8 v [2] [3] [7] -1 . 6- ? a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510na v i input voltage pin configured to provide a digital function; v dd = 1.8 v [8] [9] 0- 3 . 0v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 1.65 v ? v dd ? 1.95 v; i oh =3 ma v dd ? 0.4--v v ol low-level output voltage 1.65 v ? v dd ? 1.95 v; i ol =3 ma --0.4v i oh high-level output current v oh =v dd ? 0.4 v; 1.65 v ? v dd ? 1.95 v 3--m a i ol low-level output current v ol =0.4v 1.65 v ? v dd ? 1.95 v 3--m a www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 24 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller i ohs high-level short-circuit output current v oh =0v [10] -- ? 45 ma i ols low-level short-circuit output current v ol =v dd [10] --5 0m a i pd pull-down current v i =1.8v (v dd = 1.8 v) 10 29 90 ? a i pu pull-up current v i =0v; 1.65 v ? v dd ? 1.95 v ? 3 ? 13 ? 85 ? a v dd lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 25 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. bod disabled for all measurements. [4] irc enabled; system oscillator disabled; system pll disabled. [5] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to uart and spi0 di sabled in system configuration block. [6] irc disabled; system oscill ator enabled; system pll enabled. [7] all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 18ff. [8] including voltage on outputs in 3-state mode. [9] v dd supply voltage must be present. [10] allowed as long as the current limit does not exceed the maximum current allowed by the device. [11] to v ss . 9.1.1 analog characteristics remark: adc specifications are valid for t amb = -40 c to +85 c on hvqfn33 and wlcsp25 packages. adc specifications are valid for t amb = -10 c to +85 c on the hvqfn24 package. i 2 c-bus pins (pio0_4 and pio0_5) v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.05v dd -v i ol low-level output current v ol =0.4v; i 2 c-bus pins configured as standard mode pins 1.65 v ? v dd ? 1.95 v 2 . 5--m a i ol low-level output current v ol =0.4v; i 2 c-bus pins configured as fast-mode plus pins 1.65 v ? v dd ? 1.95 v; 1 5--m a i li input leakage current v i =v dd [11] -24 ? a oscillator pins v i(xtal) crystal input voltage ? 0.5 1.8 1.95 v v o(xtal) crystal output voltage ? 0.5 1.8 1.95 v table 5. static characteristics (single power supply ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit table 6. 8-bit adc static characteristics t amb = ? 40 ? c to +85 ? c for hvqfn33 and wlcsp25 packages. t amb = ? 10 ? c to +85 ? c for the hvqfn24 package. v dd = 1.8 v ? 5 %; 8-bit resolution. symbol parameter min typ max unit v ia analog input voltage 0 - v dd v c ia analog input capacitance - - 1 pf dnl differential non-linearity [1] [2] --? 1lsb inl integral non-linearity [3] --? 1.5 lsb e o offset error [4] --? 1lsb www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 26 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 7 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 7 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 7 . [5] the gain error (e g ) is the relative difference in percent betw een the straight line fitting the actual transfer curve after removing offset error, and the strai ght line which fits the ideal transfer curve. see figure 7 . [6] t amb = 25 ? c; maximum sampling frequency f s = 10 ksamples/s and analog input capacitance c ia = 1 pf. [7] input resistance r i depends on the sampling frequency fs: r i = 1 / (f s ? c ia ). e g gain error [5] --? 2lsb f clk(adc) adc clock frequency - - 110 khz f s sampling rate - - 10 ksamples/s r vsi voltage source interface resistance --40 k ? r i input resistance [6] [7] --2.5 m ? table 6. 8-bit adc static characteristics ?continued t amb = ? 40 ? c to +85 ? c for hvqfn33 and wlcsp25 packages. t amb = ? 10 ? c to +85 ? c for the hvqfn24 package. v dd = 1.8 v ? 5 %; 8-bit resolution. symbol parameter min typ max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 27 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 7. adc characteristics 002aag903 255 254 253 252 251 (2) (1) 256 250 251 252 253 254 255 7 123456 7 6 5 4 3 2 1 0 250 (5) (4) (3) 1 lsb (ideal) code out v dd - v ss 256 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb = www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 28 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 9.2 electrical pi n characteristics conditions: high-drive pin pio0_7; v dd = 1.8 v. fig 8. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . conditions: i 2 c-bus pins pio0_4 and pio0_5; v dd = 1.8 v; configured for fast mode plus in the iocon pio0_4 and pio0_5 registers. fig 9. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol 002aah391 0 4 8 12 16 20 1.2 1.4 1.6 1.8 2 i oh (ma) v oh (v) -40 c + 25 c + 85 c 002aah392 0 0.1 0.2 0.3 0.4 0.5 0.6 0 6 12 18 24 30 v ol (v) i ol (ma) -40 c + 25 c + 85 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 29 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller conditions: standard port pins; v dd = 1.8 v. fig 10. typical high-level output voltage v oh versus high-level output source current i oh conditions: standard port pins; v dd = 1.8 v. fig 11. typical low-level output current i ol versus low-level output voltage v ol 002aah387 0 1 2 3 4 5 6 1.2 1.4 1.6 1.8 2 i oh (ma) v oh (v) -40 c + 25 c + 85 c 002aah388 0 0.1 0.2 0.3 0.4 0.5 0.6 0 2 4 6 8 v ol (v) i ol (ma) -40 c +25 c + 85 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 30 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller conditions: standard port pins; v dd = 1.8 v. fig 12. typical pull-up current i pu versus input voltage v i conditions: standard port pins; v dd = 1.8 v. fig 13. typical pull-down current i pd versus input voltage v i 002aah394 0 0.6 1.2 1.8 2.4 3 3.6 -20 -15 -10 -5 0 5 10 v i (v) i pu p p (a) +85 c +25 c -40 c 002aah393 0 0.6 1.2 1.8 2.4 3 3.6 0 8 16 24 32 40 v i (v) i pd p p (a) -40 c +25 c +85 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 31 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 9.3 power consumption conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pull- up resistors disabled; system oscillator, system pll, irc, bod disabled; system clock prov ided by external clock. fig 14. active mode (2 mhz to 6 mhz): typical supply current i dd versus supply voltage v dd for different clock frequencies conditions: v dd = 1.8 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pull- up resistors disabled; system oscillator, system pll, irc, bod disabled; system clock prov ided by external clock. fig 15. active mode (2 mhz to 6 mhz): typical supply current i dd versus temperature for different clock frequencies 002aah297 1.65 1.7 1.75 1.8 1.85 1.9 1.95 0 0.2 0.4 0.6 0.8 1 v dd (v) i dd (ma) 2 mhz 4 mhz 6 mhz 002aah296 -40 -15 10 35 60 85 0 0.2 0.4 0.6 0.8 1 temperature (c) i dd (ma) 2 mhz 4 mhz 6 mhz www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 32 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 16. active mode: typical supply current i dd versus supply voltage for different system clock frequencies conditions: v dd = 1.8 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 17. active mode: typical supply current i dd versus temperature for different system clock frequencies 002aah299 1.65 1.7 1.75 1.8 1.85 1.9 1.95 0 2 4 6 8 v dd (v) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) 002aah298 -40 -15 10 35 60 85 0 2 4 6 8 temperature (c) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 33 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; system oscillator and system pll disabl ed; irc disabled; system clock provided by ex ternal clock. fig 18. sleep mode (2 mhz to 6 mhz): typical supply current i dd versus supply voltage v dd for different clock frequencies conditions: t amb = 25 ? c; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 19. sleep mode (12 mhz to 48 mhz): typical supply current i dd versus supply voltage v dd for different clock frequencies v dd (v) 1.65 1.95 1.85 1.75 002aag770 0.4 0.5 0.6 i dd (ma) 0.3 2 mhz 4 mhz 6 mhz v dd (v) 1.65 1.95 1.85 1.75 002aag769 1 2 3 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 34 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; v dd = 1.8 v; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 20. sleep mode (12 mhz to 48 mhz): typical supply current i dd versus temperature for different clock frequencies conditions: all oscillators and analog blo cks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 21. deep-sleep mode: typical supply current i dd versus temperature 002aah295 -40 -15 10 35 60 85 0 0.5 1 1.5 2 2.5 3 temperature (c) i dd (ma) 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) 002aah294 -40 -15 10 35 60 85 0 3 6 9 12 15 temperature (c) i dd (a) 1.95 v 1.8 v 1.65 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 35 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 9.4 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator an d pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 48 mhz. 9.5 bod static characteristics table 7. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0.26 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.18 - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.004 - - system oscillator running; pll off; independent of main clock frequency. main pll - 0.061 - adc - 0.08 0.29 clkout - 0.18 0.45 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.02 0.06 ct16b1 - 0.02 0.06 ct32b0 - 0.02 0.07 ct32b1 - 0.02 0.06 gpio - 0.23 0.88 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. iocon - 0.03 0.10 i2c - 0.04 0.13 rom - 0.04 0.15 spi0 - 0.12 0.45 uart - 0.22 0.82 wwdt - 0.02 0.06 main clock select ed as clock source for the wwdt. table 8. bod static characteristics t amb =25 ?c. symbol parameter conditions min typ max unit v th threshold voltage reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 36 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. 10.2 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 9. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 10. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ?c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 22. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 37 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 10.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc111xlv user manual . 10.4 i 2 c-bus table 11. dynamic characteristic: internal oscillators v dd ?? 1.65v to 1.95 v. symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency -20 ?c ? t amb ? +85 ?c 12 - 2.5 % 12 12 + 2.5 % mhz -40 ?c ? t amb < -20 ?c 12 - 5 % 12 12 + 5 % mhz fig 23. typical internal rc oscillator fr equency for different supply voltages v dd table 12. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz 002aah435 -40 -15 10 35 60 85 11.4 11.7 12 12.3 12.6 temperature (c) f f (mhz) (mhz) (mhz) vdd = 1.95 v vdd = 1.8 v vdd = 1.65 v table 13. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ?c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 38 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns table 13. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ?c. [2] symbol parameter conditions min max unit www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 39 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 10.5 spi interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to 85 ? c. fig 24. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 14. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit spi master (i n spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 - - ns t ds data set-up time in spi mode 1.8 v ? v dd < 1.95 v [2] 24 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] - - 10 ns t h(q) data output hold time in spi mode [2] 0-- n s www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 40 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller fig 25. spi master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 41 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller fig 26. spi slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 42 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 11. application information 11.1 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 6 : ? the adc input trace must be short and as close as possible to the lpc111xlv/lpc11xxlvuk chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. 11.2 standard i/o pad configuration figure 27 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with co nfigurable open-drain output ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 43 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 11.3 reset pad configuration fig 27. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns rc glitch filter fig 28. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 44 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 12. package outline fig 29. package outline (wlcsp25) references outline version european projection issue date iec jedec jeita wlcsp25217x232 wlcsp25_217x232_po 11-05-04 12-02-13 unit mm max nom min 0.615 0.23 0.29 2.21 2.36 1.6 0.15 0.05 a dimensions (mm are the original dimensions) wlcsp25: wafer level chip-size package; 25 bumps; 2.17 x 2.32 x 0.56 mm wlcsp25217x232 a 1 a 2 a 2 a 1 0.385 bdee y e 1 1.6 e 2 v 0.05 w 0.560 0.20 0.26 2.17 2.32 0.4 0.360 0.505 0.17 0.23 2.13 2.28 0.335 0 2 mm scale detail x c b a e 2 e 1 y x ac b ? v c ? w ball a1 index area ball a1 index area d e a e d c b a 12345 e e b www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 45 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller fig 30. package outline (hvqfn24) 0.5 1 0.2 a 1 e h b unit y e references outline version european projection issue date iec jedec jeita mm 4.1 3.9 d h 2.75 2.45 y 1 4.1 3.9 2.75 2.45 e 1 2.5 e 2 2.5 0.30 0.18 c 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot616-3 mo-220 04-11-19 05-03-10 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot616-3 hvqfn24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 712 24 19 18 13 6 1 x d e c b a e 2 terminal 1 index area terminal 1 index area ac c b v m w m 1/2 e 1/2 e e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 46 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller fig 31. package outline (hvqfn33) references outline version european projection issue date iec jedec jeita mo-220 hvqfn33f_po 11-10-11 11-10-17 unit (1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 a 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm bc 0.30 0.18 d (1) a (1) d h e (1) e h ee 1 e 2 l 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 y 1 0.05 0 2.5 5 mm scale 1/2 e ac b v c w terminal 1 index area a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 1/2 e www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 47 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 13. soldering fig 32. reflow soldering for the hvqfn24 package sot616-3 footprint information for reflow soldering of hvqfn24 package dimensions in mm ax ay bx by d slx sly spx tot spy tot spx spy gx gy hx hy 5.000 5.000 3.200 3.200 p 0.500 0.240 c 0.900 2.500 2.500 1.500 1.500 0.550 0.550 4.300 4.300 5.250 5.250 nspx nspy 22 sot616-3_fr occupied area ax bx slx gx gy hy hx aybysly p 0.025 0.025 d (0.105) spx tot spy tot nspx nspy spx spy solder land plus solder paste solder land solder paste deposit c generic footprint pattern refer to the package outline drawing for actual layout issue date 07-05-07 09-06-15 www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 48 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller fig 33. reflow soldering for the hvqfn33 (5x5) package footprint information for reflow soldering of hvqfn33 package occupied area solder paste solder land dimensions in mm p 0.5 002aag766 issue date 11-11-15 11-11-20 ax ay bx c d 5.95 5.95 4.25 0.85 by 4.25 0.27 gx 5.25 gy 5.25 hy 6.2 hx 6.2 slx sly nspx nspy 3.75 3.75 3 3 0.30 0.60 detail x c sly d slx bx ay p nspy nspx see detail x gx hx gy hy by ax www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 49 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 14. abbreviations table 15. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brown-out detect gpio general-purpose input/output jedec joint electron devices engineering council nvm non-volatile memory pll phase-locked loop spi serial peripheral interface ssi serial synchronous interface ttl transistor-transistor logic usart universal synchronous asynchronous receiver/transmitter www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 50 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 15. revision history table 16. revision history document id release date data sheet status change notice supersedes lpc111xlv_lpc11xxlvuk v.2 20121010 product data sheet - lpc111xlv_lpc11xxlvuk v.1 modifications: ? functions ct16b0_cap1/rxd added to pin pio3_4. ? functions ct16b1_cap1/txd added to pin pio3_5. ? function ct32b1_cap1 added to pin pio1_11. ? capture/clear functionality added to counter/timers. see section 7.12 . ? figure 21 ? deep-sleep mode: typical supply current i dd versus temperature ? updated. ? electrical pin characteristics data combined in section 9.2 for dual and single power supplies. ? ssp timing characteristics in slave mode removed for single power supply parts in table 14 . ? table 11 ? dynamic characteristic: internal oscillators ? and figure 23 updated. ? figure 33 corrected. ? removed dual-power supply option. all parts use a single 1.8 v +/- 10 % power supply. ? removed 10-bit adc. only t he 8-bit adc is available. ? temperature range for adc characteristics on the hvqfn24 package restricted to t amb = -10 c to +85 c. ? bod interrupt leve l 0 removed in ta b l e 8 . ? irc accuracy updated to 2.5 % accuracy for t amb = -20 c to +85 c and to 5 % accuracy for t amb = -40 c to -20 c. ? data sheet status changed to product data sheet. lpc111xlv_lpc11xxlvuk v.1 20120621 objective data sheet -- www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 51 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller 16. legal information 17. data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. www.datasheet.net/ datasheet pdf - http://www..co.kr/
lpc111xlv_lpc11xxlvuk all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights rese rved. product data sheet rev. 2 ? 10 october 2012 52 of 53 nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com www.datasheet.net/ datasheet pdf - http://www..co.kr/
nxp semiconductors lpc111xlv/lpc11xxlvuk 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 october 2012 document identifier: lpc111xlv_lpc11xxlvuk please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 11 7.1 arm cortex-m0 processor . . . . . . . . . . . . . . . 11 7.2 on-chip flash program memory . . . . . . . . . . . 11 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 11 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 nested vectored interrupt controller (nvic) . 12 7.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 7.6 iocon block . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.7 fast general purpose parallel i/o . . . . . . . . . . 13 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.9 spi serial i/o controller. . . . . . . . . . . . . . . . . . 14 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.10 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 14 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.12 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.13 system tick timer . . . . . . . . . . . . . . . . . . . . . . 16 7.14 windowed watchdog timer . . . . . . . . . . . . . 16 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.15 clocking and power control . . . . . . . . . . . . . . 17 7.15.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 17 7.15.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 18 7.15.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 18 7.15.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 19 7.15.2 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 19 7.15.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.5.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.15.5.2 deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 20 7.16 system control . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.1 start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.3 brownout detection (bod) . . . . . . . . . . . . . . 20 7.16.4 code security (code read protection - crp) 20 7.16.5 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.6 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.7 external interr upt inputs . . . . . . . . . . . . . . . . . 21 7.17 emulation and debugging . . . . . . . . . . . . . . . 21 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 22 9 static characteristics . . . . . . . . . . . . . . . . . . . 23 9.1 static characteristics . . . . . . . . . . . . . . . . . . . 23 9.1.1 analog characteristics . . . . . . . . . . . . . . . . . . 25 9.2 electrical pin characteristics. . . . . . . . . . . . . . 28 9.3 power consumption . . . . . . . . . . . . . . . . . . . . 31 9.4 peripheral power consumption . . . . . . . . . . . 35 9.5 bod static characteristics . . . . . . . . . . . . . . . 35 10 dynamic characteristics. . . . . . . . . . . . . . . . . 36 10.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 37 10.4 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 application information . . . . . . . . . . . . . . . . . 42 11.1 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 42 11.2 standard i/o pad configuration . . . . . . . . . . . 42 11.3 reset pad configuration . . . . . . . . . . . . . . . . . 43 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 44 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 50 16 legal information . . . . . . . . . . . . . . . . . . . . . . 51 17 data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 17.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 17.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 17.3 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 18 contact information . . . . . . . . . . . . . . . . . . . . 52 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 www.datasheet.net/ datasheet pdf - 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